The present invention relates to a data-erasable non-volatile semiconductor memory device, and particularly to a non-volatile semiconductor memory device improved in its data-erasing method.
An NOR-type flash memory is one of non-volatile semiconductor memory devices. For example, there is a well-known NOR-type flash memory described in the IEEE-Journal of Solid-State Circuits, vol. 27, No. 11, pp. 1540-1546, November 1992.
FIG. 1 shows a circuit configuration of the memory cell array of a general NOR-type flash memory.
In FIG. 1, a plurality of word lines WL and a plurality of bit lines BL are provided such that each word line and each bit line cross each other (although only two word lines and two bit lines are shown in the figure). Further, a memory cell formed of a non-volatile transistor is provided at each cross point between the word lines WL and bit lines BL. The control gate of each memory cell MC is connected to a corresponding work line WL, and the drain thereof is connected to a corresponding bit line BL. Further, the sources of all the memory cells MC are connected in common to a source line SL.
FIG. 2 is a cross-sectional view showing the element structure of a conventional memory cell MC forming a memory cell forming the memory cell array shown in FIG. 1. In the semiconductor region 101 consisting of a semiconductor substrate or a well region formed on the semiconductor substrate, a source 102 and a drain 103 each made of a diffusion region having a conductive type opposite to the semiconductor region 101 are formed. Further, a floating gate 104 is formed above the channel region between the source 102 and the drain 103. Further, a control gate 105 is formed above the floating gate 104, with a gate insulating film inserted therebetween. In addition, a part of the floating gate 104 overlaps the source 102 with a tunnel oxide film 106 inserted therebetween.
In the memory constructed in the structure described above, data is read in the following manner. That is, a positive voltage of, for example, +5V is applied to a selected word line WL. At this time, a sense amplifier connected to a bit line BL determines "1"/"0" depending on whether or not a current flows through a bit line BL connected to the drain of the memory cell MC. That is, in case of a memory cell of data "1", the threshold voltage is +5V or less. Therefore, when a voltage of +5V is applied to the control gate of the memory cell of the data "1", this memory cell is turned on and a drain current flows. Meanwhile, in case of a memory cell of data "0", the threshold voltage is +5V or more. Therefore, even when a voltage of +5V or more is applied to the control gate of the memory cell of the data "0", no drain current flows. Further, the current difference is detected by the sense amplifier and is outputted as sense data.
Meanwhile, data is written in the following manner. That is, a positive high voltage of, for example, +10V is applied to a selected word line WL, and a voltage of, for example, +5V is applied to the bit line BL selected for writing. In this manner, a current flows through a channel of the memory cell, and hot electrons thereby generated are injected into a floating gate 104. Further, by thus injecting the hot electrons, the threshold voltage of the memory cell into which data has thus been written increases to +5V or more.
On the other hand, during writing, a voltage of 0V is applied to bit lines which are not selected. Therefore, hot electrons are not generated in those non-selected memory cells other than the selected memory cell, so the threshold voltage of each non-selected memory cell does not change but maintains a voltage of +5V or less. Note that erasure is previously executed before writing data to maintain all the memory cells in data-storing states, and data "0" is thereafter selectively written.
Erasure of data is executed at once on a plurality of memory cells, e.g., 512 k memory cells. That is, a positive voltage of, for example, +5V is applied to the source lines SL, and a negative voltage of, for example, -7V is applied to all the word lines WL connected to the memory cells to be subjected to erasure. At this time, through the tunnel oxide film 106 in the overlapping region where the floating gate 104 of the memory cell shown in FIG. 2 overlaps the source 102 thereof, electrons are drained from the floating gate 104 by a tunneling effect, thereby achieving erasure.
Meanwhile, in a conventional memory device, the chip size has come to be reduced by downsizing elements. However, the rate of the overlapping region between the floating gate of the memory cell and the source thereof with respect to the memory size has come to increase. As a result of this, the reduction rate of the memory cell size tends to decrease.